Electronic package and fabrication method thereof

ABSTRACT

An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic packages and fabricationmethods thereof, and more particularly, to an electronic package havingwafer-level circuits and a fabrication method thereof.

2. Description of Related Art

Along with the rapid development of electronic industries, electronicproducts are developed toward the trend of multi-function and highperformance. Current chip packaging technologies have developed varioustypes of flip-chip packaging modules such as chip scale packages (CSPs),direct chip attached (DCA) packages and multi-chip module (MCM)packages.

FIGS. 1A to 1F are schematic cross-sectional views showing a method forfabricating a semiconductor package 1 according to the prior art.

Referring to FIG. 1A, a semiconductor structure is provided. Thesemiconductor structure has a silicon substrate 10, a circuit portion 11formed on the silicon substrate 10, a plurality of semiconductor chips12 flip-chip bonded to the circuit portion 10, and an underfill 13formed between the circuit portion 11 and the semiconductor chips 12.

Referring to FIG. 1B, an encapsulant 14 is formed on the circuit portion11 to encapsulate the semiconductor chips 12 and the underfill 13.

Referring to FIG. 1C, an upper portion of the encapsulant 14 is removedto expose the semiconductor chips 12.

Referring to FIG. 1D, a support member 15 is disposed on the encapsulant14 and the semiconductor chips 12. The support member 15 has an adhesivelayer 150, a silicon plate 151 and an insulating layer 152 sequentiallystacked on one another. The insulating layer 152 is made of a dielectricmaterial and formed through a chemical vapor deposition (CVD) process.

Referring to FIG. 1E, the silicon substrate 10 is removed to expose alower surface of the circuit portion 11. Then, an insulating layer 17 isformed on the lower surface of the circuit portion 11. The circuitportion 11 is partially exposed from the insulating layer 17 formounting solder balls 18.

Referring to FIG. 1F, a singulation process is performed along cuttingpaths S of FIG. 1E to obtain a plurality of semiconductor packages 1.The silicon plate 151 facilitates to enhance the rigidity of thesemiconductor packages 1 and improve the heat dissipating effect of thesemiconductor chips 12.

However, since a molding process is required to form the encapsulant 14and a grinding process is required to remove the upper portion of theencapsulant 14, the overall fabrication process is quite complicated,labor and time consuming and needs various equipment, thereby incurringa high fabrication cost.

Further, a large CTE (Coefficient of Thermal Expansion) mismatch betweenthe semiconductor chips 12 and the encapsulant 14 easily causes warpingof the overall structure before singulation.

Furthermore, since the encapsulant 14 easily absorbs moisture, it canalso result in warping of the overall structure before singulation.

As a result of warping, the semiconductor chips 12 easily crack and thesolder balls 18 easily delaminate from the circuit portion 11, thusreducing the product reliability.

Therefore, how to overcome the above-described drawbacks has becomecritical.

SUMMARY OF THE INVENTION

In view of the above-described drawbacks, the present invention providesan electronic package, which comprises: a circuit portion havingopposite first and second sides; at least an electronic element disposedon the first side of the circuit portion; and a lid member disposed onthe first side of the circuit portion to cover the electronic element,wherein a separation portion is formed between the lid member and theelectronic element.

The present invention further provides a method for fabricating anelectronic package, which comprises the steps of: providing asemiconductor structure having a carrier, a circuit portion formed onthe carrier and at least an electronic element disposed on the circuitportion, wherein the circuit portion has opposite first and secondsides, the electronic element being disposed on the first side of thecircuit portion and the second side of the circuit portion being bondedto the carrier; disposing a lid member on the first side of the circuitportion to cover the electronic element, wherein a separation portion isformed between the lid member and the electronic element; and removingthe carrier.

After removing the carrier, the above-described method can furthercomprise performing a singulation process.

In the above-described package and method, an underfill can be formedbetween the first side of the circuit portion and the electronicelement.

In the above-described package and method, the lid member can have atleast a cavity for receiving the electronic element.

In the above-described package and method, the lid member can be incontact with the electronic element.

In the above-described package and method, the lid member can be made ofa semiconductor material.

In the above-described package and method, the lid member can have asupport portion disposed on the first side of the circuit portion and abase portion supported by the support portion over the first side of thecircuit portion to cover the electronic element.

In the above-described package and method, a plurality of conductiveelements can be formed on the second side of the circuit portion.

Therefore, the present invention replaces the conventional encapsulantwith the lid member so as to simplify the fabrication process and savethe equipment cost, thereby reducing the fabrication cost. Further, thelid member facilitates to prevent warping of the overall packagestructure.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1F are schematic cross-sectional views showing a method forfabricating an electronic package according to the prior art;

FIGS. 2A to 2D are schematic cross-sectional views showing a method forfabricating an electronic package according to the present invention,wherein FIGS. 2B′ and 2B″ show different embodiments of FIG. 2B, andFIGS. 2D′ and 2D″ show different embodiments of FIG. 2D; and

FIG. 2E is a schematic cross-sectional view of a process continued fromFIG. 2D.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate thedisclosure of the present invention, these and other advantages andeffects can be apparent to those in the art after reading thisspecification.

It should be noted that all the drawings are not intended to limit thepresent invention. Various modifications and variations can be madewithout departing from the spirit of the present invention. Further,terms such as “first”, “second”, “on”, “a” etc. are merely forillustrative purposes and should not be construed to limit the scope ofthe present invention.

FIGS. 2A to 2D are schematic cross-sectional views showing a method forfabricating an electronic package 2 according to the present invention.

Referring to FIG. 2A, a semiconductor structure 2 a is provided. Thesemiconductor structure 2 a has a carrier 20, a circuit portion 21formed on the carrier 20, a plurality of electronic elements 22 disposedon the circuit portion 21, and an underfill 23 formed between thecircuit portion 21 and the electronic elements 22.

In the present embodiment, the carrier 20 is made of a semiconductormaterial such as silicon.

Each of the electronic elements 22 is an active element such as asemiconductor chip, a passive element such as a resistor, a capacitor oran inductor, or a combination thereof. In the present embodiment, eachof the electronic elements 22 is an active element having an activesurface 22 a and an inactive surface 22 b opposite to the active surface22 a.

The circuit portion 21 has a plurality of dielectric layers 210 and aplurality of circuit layers 211 stacked alternately. The circuit portion21 has a first side 21 a and a second side 2 lb opposite to the firstside 21 a. The active surfaces 22 a of the electronic elements 22 arebonded to the circuit layer 211 on the first side 21 a of the circuitportion 21 through a plurality of conductive bumps 221, and theconductive bumps 221 are encapsulated by the underfill 23. The secondside 21 b of the circuit portion 21 is bonded to the carrier 20.Further, the second side 21 b of the circuit portion 21 has a pluralityof conductive pads 212.

The circuit layers 211 are wafer-level circuits instead of packagingsubstrate-level circuits. Currently, the packaging substrate-levelcircuits have a minimum line width/pitch of 12/12 um, but thewafer-level circuits have a minimum line width/pitch of 3/3 um.

Referring to FIG. 2B, a lid member 25 is disposed on the first side 21 aof the circuit portion 21 to cover the electronic elements 22 and theunderfill 23. The lid member 25 has at least a cavity 26 for receivingthe electronic elements 22 therein.

In the present embodiment, a separation portion A is formed between thelid member 25 and the electronic elements 22. In particular, theseparation portion A is formed between the lid member 25 and theinactive and side surfaces 22 b, 22 c of the electronic elements 22. Inanother embodiment, referring to FIG. 2B′, a base portion 250 of the lidmember 25′ is in contact with the inactive surfaces 22 b of theelectronic elements 22, and the separation portion A is only formedbetween the lid member 25′ and the side surfaces 22 c of the electronicelements 22.

The lid member 25 is made of a semiconductor material. For example, thelid member 25 is a silicon wafer. The lid member 25 has a supportportion 251 disposed on the first side 21 a of the circuit portion 21,and a base portion 250 supported by the support portion 251 over thefirst side 21 a of the circuit portion 21 to cover the electronicelements 22 and the underfill 23. To fabricate the lid member 25, asilicon wafer can be etched to form the cavity 26 and the supportportion 251, and the support portions 251 are side walls of the cavity26.

In another embodiment, referring to FIG. 2B″, the lid member 25″ has aplurality of cavities 26′ each receiving one electronic element 22.

Referring to FIG. 2C, the carrier 20 is removed to expose the secondside 21 b of the circuit portion 21 and the conductive pads 212. Then, aplurality of conductive elements 28 such as solder balls are formed onthe second side 21 b of the circuit portion 21.

In the present embodiment, before formation of the conductive elements28, an insulating layer 27 is formed on the second side 21 b of thecircuit portion 21. The insulating layer 27 has a plurality of openings270 exposing the conductive pads 212, and the conductive elements 28 areformed on the conductive pads 212.

Referring to FIG. 2D, a singulation process is performed along cuttingpaths S of FIG. 2C (i.e., along the support portion 251 of the lidmember 25) to obtain a plurality of electronic packages 2.

Alternatively, the singulation process can be performed before formationof the insulating layer 27 and the conductive elements 28.

If the process is continued form FIGS. 2B′, an electronic packages 2′ ofFIG. 2D′ is obtained. Similarly, if the process is continued form FIG.2B″, an electronic packages 2″ of FIG. 2D″ is obtained.

In a subsequent process, referring to FIG. 2E, the electronic package 2is further disposed on an electronic device 29 such as a circuit boardthrough the conductive elements 28, and an underfill 290 is formedbetween the electronic package 2 and the electronic device 29 to secureand protect the conductive elements 28.

Therefore, by replacing with the conventional encapsulant with the lidmember 25, 25′, 25″, the present invention dispenses with theconventional molding and grinding processes and hence simplifies thefabrication process, saves labor and time and reduces the equipmentcost, thereby greatly reducing the fabrication cost.

Further, since there is a very small CTE mismatch between the lid member25, 25′, 25″ and the electronic elements 22, the present inventionprevents warping of the overall structure before singulation andimproves the product yield.

Furthermore, the lid member 25, 25′, 25″ does not absorb moisture. Assuch, the present invention avoids warping of the overall structure (forexample, the structure of FIG. 2C) after the carrier 20 is removed.

In addition, after the carrier 20 is removed, the rigidity of the lidmember 25, 25′, 25″ facilitates to reduce the degree of warping of theoverall structure that may be caused by a large CTE mismatch between thecircuit portion 21, the electronic elements 22 and the underfill 23.

The present invention prevents warping of the overall structure so as toprevent cracking of the electronic elements 22 and delamination of theconductive elements 28, thereby improving the product reliability.

The present invention further provides an electronic package 2, 2′, 2″,which has: a circuit portion 21 having opposite first and second sides21 a, 21 b; at least an electronic element 22 disposed on the first side21 a of the circuit portion 21; and a lid member 25, 25′, 25″ disposedon the first side 21 a of the circuit portion 21 to cover the electronicelement 22, wherein a separation portion A is formed between the lidmember 25, 25′, 25″ and the electronic element 22.

The lid member 25, 25′, 25″ can have at least a cavity 26, 26′ forreceiving the electronic element 22.

The lid member 25, 25′, 25″ can be made of a semiconductor material.

In an embodiment, the lid member 25′ is in contact with the electronicelement 22.

In an embodiment, the lid member 25, 25′, 25″ has a support portion 251disposed on the first side 21 a of the circuit portion 21 and a baseportion 250 supported by the support portion 251 over the first side 21a of the circuit portion 21 to cover the electronic element 22.

In an embodiment, the electronic package 2, 2′, 2″ further has anunderfill 23 formed between the first side 21 a of the circuit portion21 and the electronic element 22.

In an embodiment, the electronic package 2, 2′, 2″ further has aplurality of conductive elements 28 formed on the second side 21 b ofthe circuit portion 21.

Therefore, the present invention replaces the conventional encapsulantwith the lid member so as to simplify the fabrication process and savethe equipment cost, thereby reducing the fabrication cost. Further, thelid member facilitates to prevent warping of the overall packagestructure.

The above-described descriptions of the detailed embodiments are only toillustrate the preferred implementation according to the presentinvention, and it is not to limit the scope of the present invention.Accordingly, all modifications and variations completed by those withordinary skill in the art should fall within the scope of presentinvention defined by the appended claims.

What is claimed is:
 1. An electronic package, comprising: a circuitportion having opposite first and second sides; at least an electronicelement disposed on the first side of the circuit portion; and a lidmember disposed on the first side of the circuit portion to cover theelectronic element, wherein a separation portion is formed between thelid member and the electronic element.
 2. The package of claim 1,wherein the lid member has at least a cavity for receiving theelectronic element.
 3. The package of claim 1, wherein the lid member isin contact with the electronic element.
 4. The package of claim 1,wherein the lid member is made of a semiconductor material.
 5. Thepackage of claim 1, wherein the lid member has a support portiondisposed on the first side of the circuit portion and a base portionsupported by the support portion over the first side of the circuitportion to cover the electronic element.
 6. The package of claim 1,further comprising an underfill formed between the first side of thecircuit portion and the electronic element.
 7. The package of claim 1,further comprising a plurality of conductive elements formed on thesecond side of the circuit portion.
 8. A method for fabricating anelectronic package, comprising the steps of: providing a semiconductorstructure having a carrier, a circuit portion formed on the carrier andat least an electronic element disposed on the circuit portion, whereinthe circuit portion has opposite first and second sides, the electronicelement being disposed on the first side of the circuit portion and thesecond side of the circuit portion being bonded to the carrier;disposing a lid member on the first side of the circuit portion to coverthe electronic element, wherein a separation portion is formed betweenthe lid member and the electronic element; and removing the carrier. 9.The method of claim 8, wherein the semiconductor structure further hasan underfill formed between the first side of the circuit portion andthe electronic element.
 10. The method of claim 8, wherein the lidmember has at least a cavity for receiving the electronic element. 11.The method of claim 8, wherein the lid member is in contact with theelectronic element.
 12. The method of claim 8, wherein the lid member ismade of a semiconductor material.
 13. The method of claim 8, wherein thelid member has a support portion disposed on the first side of thecircuit portion and a base portion supported by the support portion overthe first side of the circuit portion to cover the electronic element.14. The method of claim 8, after removing the carrier, furthercomprising forming a plurality of conductive elements on the second sideof the circuit portion.
 15. The method of claim 8, after removing thecarrier, further comprising performing a singulation process.